iWave iW-RainboW-G24M Arria 10 FPGA SOM

Arria 10 FPGA device compatibility (GX270, GX320, GX480, GX570, GX660, GX900, GX1150)
With upto 1150K Logic Elements and 24 High Speed transceivers
4-GB DDR4 RAM (64bit) & 2-GB DDR4 RAM for FPGA
24 high-speed transceivers @ 17.4Gbps
48/96 LVDS from BANK 3B & 3C and 93 SE from BANK 2A & 3A
Dual 240 Pin Board to Board Connector
Variable IO voltage support from PMIC
Industrial Grade operation
10+ Years Longevity

Description

Compatible Arria10 FPGA Family – GX270, GX320, GX480, GX570, GX660, GX900, GX1150
- Up to 1150K Logic elements
- High Speed Transceivers x 24 @ 17.4 Gbps
2-GB DDR4 RAM (32bit) from FPGA
4-GB DDR4 RAM (64bit) from FPGA (only in GX480 or higher family devices)
Configuration Flash for FPGA
Other On SOM features
- JTAG Header
- 5V-FAN Header
- FPGA AS Header
- FPGA Configuration Selection Switch

From connector 1 interface	FPGA High Speed Transceivers (upto 17.4Gbps) x 16 FPGA IOs & General Purpose Clocks – Bank2A Up to 21 LVDS/46SE IOs One General Purpose Clock Input LVDS Pair/Single Ended Two General Purpose Clock Output LVDS Pairs/Single Ended FPGA IOs & General Purpose Clocks – Bank3A Up to 22 LVDS/47SE IOs Two General Purpose Clock Input LVDS Pairs/Single Ended Two General Purpose Clock Output LVDS Pairs/Single Ended
From connector 2 interface	Gigabit Ethernet x 1 Port (through On-SOM Gigabit Ethernet PHY from Bank2L IOs) USB OTG x 1 Port (through On-SOM USB ULPI PHY from Bank2L IOs) Upto 20 Single-Ended IOs FPGA AS Interface (Optional) FPGA High-Speed Transceivers (up to 17.4Gbps) x 8 FPGA IOs & General Purpose Clocks – Bank3B Up to 24 LVDS IOs/48SE IOs Two General Purpose Clock Input LVDS Pairs/Single Ended Two General Purpose Clock Output LVDS Pairs/Single Ended FPGA IOs & General Purpose Clocks – Bank3C Up to 24 LVDS IOs/48SE IOs Two General Purpose Clock Input LVDS Pairs/Single Ended Two General Purpose Clock Output LVDS Pairs/Single Ended JTAG Interface

From connector 1 interface

- Up to 21 LVDS/46SE IOs
- One General Purpose Clock Input LVDS Pair/Single Ended
- Two General Purpose Clock Output LVDS Pairs/Single Ended
FPGA IOs & General Purpose Clocks – Bank3A
- Up to 22 LVDS/47SE IOs
- Two General Purpose Clock Input LVDS Pairs/Single Ended
- Two General Purpose Clock Output LVDS Pairs/Single Ended

From connector 2 interface

Gigabit Ethernet x 1 Port (through On-SOM Gigabit Ethernet PHY from Bank2L IOs)
USB OTG x 1 Port (through On-SOM USB ULPI PHY from Bank2L IOs)
Upto 20 Single-Ended IOs
FPGA AS Interface (Optional)
FPGA High-Speed Transceivers (up to 17.4Gbps) x 8
FPGA IOs & General Purpose Clocks – Bank3B
- Up to 24 LVDS IOs/48SE IOs
- Two General Purpose Clock Input LVDS Pairs/Single Ended
- Two General Purpose Clock Output LVDS Pairs/Single Ended
FPGA IOs & General Purpose Clocks – Bank3C
- Up to 24 LVDS IOs/48SE IOs
- Two General Purpose Clock Input LVDS Pairs/Single Ended
- Two General Purpose Clock Output LVDS Pairs/Single Ended
JTAG Interface

Serdecznie zapraszamy do kontaktu!